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rev.01 16mb sdram 1/18 ordering information em 48 1 m 16 2 2 v t a ? 6 l eorex memory edo/fpm : 40 d-rambus : 41 ddrsdram : 42 ddrsgram : 43 sgram : 46 sdram : 48 power blank : standard l : low power i : indus trial f : pb free package density 16m : 16 mega bits 8m : 8 mega bits 4m : 4 mega bits 2m : 2 mega bits 1m : 1 mega bit refresh 1 : 1k, 8 : 8k 2 : 2k, 6 :16k 4 : 4k bank 2 : 2bank 6 : 16bank 4 : 4bank 3 : 32bank 8 : 8bank revision a : 1s t b : 2nd c : 3rd d : 4th interface v : 3.3v r : 2.5v package min cycle time ( max freq.) -5 : 5ns ( 200mhz ) -6 : 6ns ( 167mhz ) -7 : 7ns ( 143mhz ) -75 : 7.5ns ( 133mhz ) -8 : 8ns ( 125mhz ) -10 : 10ns ( 100mhz ) c: csp b: ubga t: tsop q: tqfp p: pqfp ( qfp ) organization 8 : x8 9 : x9 16 : x16 18 : x18 32 : x32
rev.01 16mb sdram 2/18 feature ? fully synchronous to positive clock edge ? single 3.3v +/- 0.3v power supply ? lvttl compatible with multiplexed address ? programmable burst length (b/ l) - 1,2,4,8 or full page ? programmable cas latency (c/ l) - 2 or 3 ? data mask (dqm) for read / write masking ? programmable wrap sequence - sequential ( b/ l = 1/2/4/8/full page ) - interleave ( b/ l = 1/2/4/8 ) ? burst read with single-bit write operation ? all inputs are sampled at the rising edge of the system clock. ? auto refresh and self refresh ? 2,048 refresh cycles / 32ms description the em481m1622vta is synchronous dynamic random access memory (sdram) organized as 512k x 2 banks x 16 bits. all inputs and outputs are synchronized with the positive edge of the clock. the 16mb sdram uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3v low power memory system. it also provides auto refresh with power saving / down mode. all inputs and outputs voltage levels are compatible with lvttl . * eorex reserves the right to change products or specification without notice. 16mb ( 2banks ) synchronous dram em481m1622vta (1mx16)
rev.01 16mb sdram 3/18 50pin tsop-ii pin assignment ( top view ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 v dd dq0 dq1 v ssq dq2 dq3 v ddq dq4 dq5 v ssq dq6 dq7 v ddq ldqm /we /cas /ras /cs ba a10 a0 a1 a2 a3 v dd v ss dq15 dq14 v ssq dq13 dq12 v ddq dq11 dq10 v ssq dq9 dq8 v ddq nc udqm clk cke nc a9 a8 a7 a6 a5 a4 v ss
rev.01 16mb sdram 4/18 pin name pin function clk system clock master clock input(active on the positive rising edge) /cs chip select selects chip when active cke clock enable activates the clk when ?h? and deactivates when ?l?. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. a0 ~ a10 address row address (a0 to a10) is determined by a0 to a10 level at the bank active command cycle clk rising edge. ca(ca0 to ca7) is determined by a0 to a7 level at the read or write command cycle clk rising edge. and this column address becomes burst access start address. a10 defines the pre-charge mode. when a10 = high at the pre-charge command cycle, all banks are pre-charged. but when a10 = low at the pre-charge command cycle, only the bank that is selected by ba is pre-charged. /ras row address strobe latches row addresses on the positive rising edge of the clk with /ras ?l?. enables row access & pre-charge. /cas column address strobe latches column addresses on the positive rising edge of the clk with /cas low. enables column access. /we write enable latches column addresses on the positive rising edge of the clk with /cas low. enables column access. udqm /ldqm data input/output mask dqm controls i/o buffers. dq0 ~ 15 data input/output dq pins have the same function as i/o pins on a conventional dram. v dd /v ss power supply/ground v dd and v ss are power supply pins for internal circuits. pin descriptions ( simplified ) ba bank address selects which bank is to be active. nc no connection this pin is recommended to be left no connection on the device. v ddq /v ssq power supply/ground v ddq and v ssq are power supply pins for the output buffers.
rev.01 16mb sdram 5/18 burst counter row add. buffer col. add. buffer col. decoder s/a & i/o gating block diagram a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 ba timing register clk cke /cs /ras /cas /we dqm row decoder memory array address register mode register set auto/self refresh counter col. add. counter write dqm control data in data out read dqm control dqi dqm dqm
rev.01 16mb sdram 6/18 idle row acti ve acti ve power down power down cbr refresh self refresh mo d e register set write writea read reada read suspend reada suspend write suspend writea suspend precharge power on simplified state diagram s e l f s e l f e x i t r e f m r s c k e c k e a c t c k e c k e b s t r e a d r e a d c k e c k e c k e c k e w r i t e r e a d w r i t e w i t h r e a d w i t h c k e c k e c k e c k e p r e c h a r g e p r e p r e w r i t e m a n u a l i n p u t a u t o m a t i c s e q u e n c e
rev.01 16mb sdram 7/18 ba a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 operation mode cas latency bt burst length a2 a1 a0 sequential burst length interleave 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved a3 0 burst type interleave 1 sequential a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 2 0 1 0 3 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved ba a10 a9 a8 a7 0 0 0 0 0 0 0 1 0 0 operation mode normal burst read with single-bit write address input for mode register set
rev.01 16mb sdram 8/18 a2 a1 a0 interleave addressing burst length x x 0 0 1 2 x x 1 1 0 x 0 0 0 1 2 3 4 x 0 1 1 0 3 2 x 1 0 2 3 0 1 x 1 1 3 2 1 0 0 0 0 0 1 2 3 4 5 6 7 8 0 0 1 1 0 3 2 5 4 7 6 burst type ( a3 ) sequential addressing 0 1 1 0 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 0 1 0 2 3 0 1 6 7 4 5 0 1 1 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 1 0 1 5 4 7 6 1 0 3 2 1 1 0 6 7 4 5 2 3 0 1 1 1 1 7 6 5 4 3 2 1 0 n n n - 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 cn cn+ 1 cn+ 2 ?... full page * * page length is a function of i/o organization and column addressing x16 (ca0 ~ ca7) : full page = 256 bits
rev.01 16mb sdram 9/18 command symbol cke ignore command desl no operation nop truth table 1. command truth table h h x n-1 n /cs h l x /ras x h /cas x h /we x h ba x x a10 x x a9~a0 x x burst stop bsth read rea d h h x l l x h h h l l h x v x l x v read with auto pre-charge rea da write writ h h x l l x h h l l h l v v h l v v write with auto pre-charge writa bank activate act h h x l l x l l h h h h v v h v v v pre-charge select bank pre h l x l h l v l x pre-charge all banks pa l l mode register set mrs h h x l l x l l h l l l x l h l x v no t e : h = high level, l = low level, x = high or low level (don't care), v = valid data input command symbol cke 2. dqm truth table n-1 n /cs data w rite / output enable enb data mask / output disable ma sk h h x h l x upper byte w rite enable / output enable bsth read rea d h h x l l x read w ith auto pre-charge rea da write writ h h x l l x write w ith auto pre-charge writa bank activate act h h x l l x pre-charge select bank pre h l x pre-charge all banks pa l l mode register set mrs h h x l l x no t e : h = high level, l = low level, x = high or low level (don't care), v = valid data input command symbol cke activating an y 3. cke truth table h l l n-1 n /cs x x l /ras x x /cas x x /we x x addr. x x clock suspend idle ref l h h x l h x l x l x h x x idle self self refresh h l l l l h l h l h h h x x idle power down h l l x x h x x x x x x x x re m ar k h = high level, l = low level, x = high or low level (don't care) command clock suspend mode entry clock suspend mode clock suspend mode exit cbr refresh command self refresh entry self refresh exit pow er dow n entry pow er dow n exit l h h x x x x ( em481m1622vt ) ( em481m1622vt )
rev.01 16mb sdram 10/18 current state addr. idle x x 4. operative command table action nop or pow er dow n nop or pow er dow n notes 2 2 ba/ca/a10 ba/ca/a10 illegal illegal 3 3 ba/ra row ac tiv ating ba, a10 x nop refresh or self refresh 4 re m ar k h = high level, l = low level, x = high or low level (don't care) /cs h l /r x h /c x h /w x x l l h h l l h l l l h h l l l l h l l h command desl nop or bst rea d/rea da writ/writa act pre/ pa l l ref/self op-code mode register accessing l l l l mrs row active x x nop nop ba/ca/a10 ba/ca/a10 begin read : determine ap begin w rite : determine ap 5 5 ba/ra illegal 3 ba, a10 x precharge illegal 6 4 h l x h x h x x l l h h l l h l l l h h l l l l h l l h desl nop or bst rea d/rea da writ/writa act pre/ pa l l ref/self op-code illegal l l l l mrs re ad x x continue burst to end row ac tiv e continue burst to end row ac tiv e x ba/ca/a10 burst stop row ac tiv e terminate burst, new read : determine ap 7 ba/ca/a10 terminate burst, start w rite : determine ap 7, 8 ba/ra ba/a 10 illegal terminate burst, pre-charging 3 4 h l x h x h x h l l h h h l l h l l l l l l l l h h h l desl nop bst rea d/rea da writ/writa act pre/ pa l l x illegal l l l h ref/self write x x continue burst to end write recovering continue burst to end write recovering x ba/ca/a10 burst stop row ac tiv e terminate burst, start read : determine ap 7, 8 7,8 ba/ca/a10 terminate burst, new w rite : determine ap 7 7 ba/ra ba/a 10 illegal terminate burst, pre-charging 3 9 h l x h x h x h l l h h h l l h l l l l l l l l h h h l desl nop bst rea d/rea da writ/writa act pre/ pa l l x illegal l l l h ref/self op-code illegal l l l l mrs op-code illegal l l l l mrs
rev.01 16mb sdram 11/18 current state addr. re ad w it h ap x x action continue burst to end precharging continue burst to end precharging notes x ba/ca/a10 illegal illegal 3 ba/ra illegal 3 ba, a10 x illegal illegal 3 re m ar k h = high level, l = low level, x = high or low level (don't care), ap = auto precharge /cs h l /r x h /c x h /w x h l l h h h l l h l l h h l l l l h l l h command desl nop bst rea d/rea da act pre/ pa l l ref/self op-code illegal l l l l mrs ba/ca/a10 illegal 3 l h l l writ/writa write w ith ap x x burst to end write recovering w ith auto precharge continue burst to end write recovering w ith auto precharge x ba/ca/a10 illegal illegal 3 ba/ra illegal 3 ba, a10 x illegal illegal 3 h l x h x h x h l l h h h l l h l l h h l l l l h l l h desl nop bst rea d/rea da act pre/ pa l l ref/self op-code illegal l l l l mrs ba/ca/a10 illegal 3 l h l l writ/writa pre charging x x nop enter idle after t rp nop enter idle after t rp x ba/ca/a10 illegal illegal 3 ba/ra illegal 3 ba, a10 x nop enter idle after t rp illegal h l x h x h x h l l h h h l l h l l h h l l l l h l l h desl nop bst rea d/rea da act pre/ pa l l ref/self op-code illegal l l l l mrs ba/ca/a10 illegal 3 l h l l writ/writa row activating x x nop enter idle after t rcd nop enter idle after t rcd x ba/ca/a10 illegal illegal 3 ba/ra illegal 3,10 ba, a10 x illegal illegal 3 h l x h x h x h l l h h h l l h l l h h l l l l h l l h desl nop bst rea d/rea da act pre/ pa l l ref/self op-code illegal l l l l mrs ba/ca/a10 illegal 3 l h l l writ/writa
rev.01 16mb sdram 12/18 current state addr. write recovering x x action nop enter row active after t dpl nop enter row active after t dpl notes x ba/ca/a10 nop enter row active after t dpl start read, determine ap ba/ra illegal 3 ba, a10 x illegal illegal 3 re m ar k h = high level, l = low level, x = high or low level (don't care), ap = auto precharge /cs h l /r x h /c x h /w x h l l h h h l l h l l h h l l l l h l l h command desl nop bst rea d/rea da act pre/ pa l l ref/self op-code illegal l l l l mrs ba/ca/a10 new w rite, determine ap 8 l h l l writ/writa write recovering with ap x x nop enter precharge after t dpl nop enter precharge after t dpl x ba/ca/a10 nop enter precharge after t dpl illegal 3,8 ba/ra illegal 3 ba, a10 x illegal illegal h l x h x h x h l l h h h l l h l l h h l l l l h l l h desl nop bst rea d/rea da act pre/ pa l l ref/self op-code illegal l l l l mrs ba/ca/a10 illegal 3 l h l l writ/writa refreshing x x nop enter idle af ter t rc nop enter idle af ter t rc x x illegal illegal h l x h x h x x l l h l l h x x desl nop/ bst rea d/writ a ct/ pre/ pa l l x illegal l l l x ref/self/mrs mode register accessing x x nop nop x x illegal illegal h l x h x h x h l l h h h l l x desl nop bst rea d/writ x illegal l l x x a ct/ pre/ pa l l / ref/self/mrs no t e s 1. all entries assume that cke w as active (high level) during the preceding clock cycle. 2. if all banks are idle, and cke is inactive (low level), sdram w ill enter pow er dow n m ode. all input buffers except cke w ill be disabled. 3. illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. 4. if all banks are idle, and cke is inactive (low level), sdram w ill enter self ref resh mode. all input buffers except cke w ill be disabled. 5. illegal if t rcd is not satis f ied. 6. illegal if t ras is not satis f ied. 7. must satisfy burst interrupt condition. 8. must satisfy bus contention, bus turn around, and/or w rite recovery requirements. 9. must mask preceding data w hich don't satisfy t dpl . 10. illegal if t rrd is not satisfied.
rev.01 16mb sdram 13/18 current state addr. se lf re fre s h x x 5. command truth table for cke action invalid, clk (n ? 1) w ould exit self refresh self refresh recovery notes x x self refresh recovery illegal x illegal x maintain self ref resh re m ar k : h = high level, l = low level, x = high or low level (don't care) /cs x h /r x x /c x x /w x x l l h h h l x x l l x x x x x x se lf re fre s h recovery x x idle after t rc idle after t rc x x illegal illegal x illegal x x illegal illegal h l x h x h x x l l h l l x x x h x x x l l h h h l x x x illegal l l x x bo t h b an k s idle refer to operations in operative command table refer to operations in operative command table refer to operations in operative command table x ref r es h op-code refer to operations in operative command table refer to operations in operative command table h l x h x x x x l l h x l l l h l h l x l x l x refer to operations in operative command table l h x x refer to operations in operative command table l l h x n-1 h l l l l l h h h h h h h h h h h h h h h h n x h h h h l h h h h l l l l h h h h h l l l cke power down x x invalid, clk(n-1) w ould exit pow er dow n exit pow er dow n idle x maintain pow er dow n mode x x x x x x x x x x x x h l l x h l x self ref resh 1 l l l h op-code refer t o operations in operative command table l l l l x pow er dow n 1 x x x x h h l l l x row active x refer to operations in operative command table x x x x h x x pow er dow n 1 x x x x l x any state other than listed above x refer to operations in operative command table begin clock suspend next cycle 2 x exit clock suspend next cycle x maintain clock suspend x x x x x x x x x x x x x x x x h h l l h l h l no t e s 1. self refresh can be entered only from the both banks idle state. pow er dow n can be entered only from both banks idle or row active state. 2. must be legal command as defined in operative command table.
rev.01 16mb sdram 14/18 absolute maximum ratings symbol item rating units v in , v out input, output voltage -0.3 ~ 4.6 v v dd , v ddq power supply voltage -0.3 ~ 4.6 v t op operating temperature 0 ~ 70 c t stg storage temperature -55 ~ 150 c p d power dissipation 1 w i os short circuit current 50 ma recommended dc operation conditions ( ta = 0 ~ 70c ) symbol parameter min. units v dd power supply voltage 3.0 v v ddq power supply voltage (for i/o buffer) 3.0 v v ih input logic high voltage 2.0 v v il input logic low voltage -0.3 v no t e : caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliab ility . typical 3.3 3.3 max. 3.6 3.6 v dd +0.3 0.8 no t e : 1. all voltage referred to v ss . 2. v ih (max) = 5.6v for pulse w idth 3ns 3. v il (min) = -2.0v for pulse w idth 3ns capacitance ( vcc =3.3v, f = 1mhz, ta = 25c ) symbol parameter min. units c clk clock capacitance 2.5 pf c i input capacitance for clk, cke, address, /cs, /ras, /cas, /we, dqml,dqmu 2.5 pf max. 4.0 5.0 c o input/output capacitance 4.0 pf 6.5
rev.01 16mb sdram 15/18 recommended dc operating conditions ( vdd = 3.3v +/- 0.3 v, ta = 0 ~ 70 c , ta = -40 to 85c for 6i) no t e : 1. icc1 depends on output loading and cycle rates. specified values are obtained w ith the output open. input signals are changed only one time during tck(min) 2. icc4 depends on output loading and cycle rates. specified values are obtained w ith the output open. input signals are changed only one time during tck(min) 3. input signals are changed only one time during tck(min) 4. standard pow er version. 5. * low pow er version. precharge standby current in power down mode precharge standby current in non-power down mode active standby current in non-power down mode operating current (burst mode) refresh current self refresh current active standby current in power down mode ma ma cke v il (min), t ck = 15ns ,/ cs v ih (min) input signals are changed one time during 30ns cke v il (min), t ck = input signals are stable i cc3n i cc3ns 30 20 cke v il (max.), t ck = operating current parameter test condition burst length = 1, t rc t rc (min), iol = 0 ma, one bank active cke v il (max.), t ck = 15 ns symbol i cc1 i cc2p i cc2ps max 100 5 2 / 0.7* 2 / 0.7* ma ma units ma notes 1 5 5 90 6/6i/6l 80 7/7l cke v il (min.), t ck = 15 ns, /cs v ih (min.) input signals are changed one time during 30ns cke v il (min.), t ck = input signals are stable i cc2n i cc2ns 20 8 ma ma ma ma ma 2 3 4 t ccd = 2clks , i ol = 0 ma t rc t rc (min.) cke 0.2v i cc4 i cc5 i cc6 130 2 120 180 160 140 110 ma ma cke v il (max), t ck = 15ns cke v il (max), t ck = i cc3p i cc3ps 5 5 0.3 5 cl=3 cl=2
rev.01 16mb sdram 16/18 ac operating test conditions ( vdd = 3.3v +/- 0.3 v, ta = 0 ~ 70 c , ta = -40 to 85c for 6i ) output reference level 1.4v / 1.4v output load see diagram as below input signal level 2.4v / 0.4v transition time of input signals 2ns input reference level 1.4v z = 50 ? 50pf 50 ? v tt = 1.4v output parameter test condition symbol max. unit min. input leakage current 0 v i v dd q, v ddq =v dd all other pins not under test=0 v i il +0.5 ua -0.5 output leakage current 0 v o v dd q, dout is disabled i ol +0.5 ua -0.5 high level output voltage io = -4m a v oh v 2.4 low level output voltage io = +4ma v ol v 0.4 recommended dc operating conditions ( continued )
rev.01 16mb sdram 17/18 parameter symbol units -6/6i/6l -7/7l min. min. -5 min. max. max. max. clock cycle time acces s tim e from clk data-out hold time data-out high impedance time clk high level width clk low level width input s etup tim e input hold tim e active to active command period active to precharge command period precharge to active command period ac tive to r ead /wr ite d e l a y ti m e active(one) to active(another) command read/write command to read/write command cl = 3 cl = 2 cl = 3 cl = 2 cl = 3 cl = 2 cl = 3 cl = 2 t ck t ac t ch t cl t oh t hz t lz t is t ih t rc t ras t rp t rcd t rrd t ccd 7 7.5 5.5 5.5 1.5 2 5 4.5 1.5 1.5 1.5 5 0 1.5 54 40 18 14 10 1 100k 6 2 2 0 1.5 60 42 18 18 12 100k 6 5 7 8 5.5 5 2.75 2.75 2 7 1 1 100k 65 45 18 20 14 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns clk data-in to precharge command t dpl 222clk data-out to high impedance from precha rge c o mma n d data-in to burst stop command refresh time(2,048 cycle) cl = 3 cl = 2 t bdl t roh t ref 1 3 32 1 3 32 1 3 2 32 clk clk clk ms data-out low impedance time operating ac characteristics ( vdd = 3.3v +/- 0.3 v, ta = 0 ~ 70 c , ta = -40 to 85c for 6i) notes 2 2 2 2 2 all voltages referenced to vss. note : 1. t hz defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. 2. these parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows : the number of clock cycles = specified value of timing/clock period (count fractions as a whole number) 2 1 1 1.5 2 1 1 2 2 2 2
rev.01 16mb sdram 18/18 package dimension

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